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Lattice Semiconductor
Functional Description
Programming the MODE and TX_RX_CTL registers can control the Receive MAC operation. The various events
that occur during the reception of a frame are logged into the rx_stat_vector signal and the TX_RX_STS register.
At the end of reception, the rx_stat_en signal is asserted to qualify the rx_stat_vector signal. The TSMAC IP core
can report a wealth of information such as
? FIFO overflow
? CRC error
? Receive error
? Short frame reception
? Long frame reception
? IPG violation
By default, the entire frame, except the preamble and SFD bytes, is sent to the FIFO via the Rx MAC application
interface signals. If the user does not want to receive the FCS, the core can be programmed to strip the FCS field
as well as any PAD bytes in the frame and send the rest to the FIFO.
The Rx MAC section operates on the rxmac_clk derived from the rx_clk sourced from the PHY. All the signals on
the Receive MAC FIFO interface are synchronous to this clock.
The Rx MAC is disabled while Rx_en is low (Bit_2 of the MODE register) and should only be enabled after the
associated registers are properly initialized.
Receiving Frames
The frames received by the Rx MAC are analyzed and the Preamble and SFD bytes are stripped off the frame
before it is transferred to an external FIFO. The client data interface between the MAC and the FIFO is eight bits
wide.
The default behavior of the MAC is to transfer the unmodified frame after stripping off the Preamble and SFD bytes.
This behavior can be changed by setting bit [1] of the TX_RX_CTL register. When bit [1] is set, the Rx MAC strips
the Preamble, SFD, FCS bytes and the PAD bytes, if any. Note that the Rx MAC assumes a received frame has
PAD bytes if a 64 byte packet is received with its Length/Type field set to a value of less than 46 bytes.
Once the frame is ready to be written into the FIFO, the Rx MAC asserts the rx_write signal, then presents the data
on the rx_dbout bus. The rx_write signal is asserted as long as the frame is being written. After transferring the
entire frame into the FIFO, the Rx MAC asserts rx_eof indicating the end of the frame. If the frame is received with
errors, rx_error is asserted along with rx_eof. If the frame is received with no errors, rx_error remains de-asserted.
In either case, a rich set of statistics vectors is presented, containing information about the frame that was
received. The statistics vector bus, rx_stat_vector, is qualified by the assertion of rx_stat_en.
If the RxFIFO becomes full, rx_fifo_full is asserted and the frame data is lost. Therefore, the FIFO full condition
must be avoided at all times. The rx_fifo_error signal will be asserted along with rx_eof for all frames written into
the FIFO while it is full.
The Rx MAC goes to the IDLE state when it is done receiving the frame. This is indicated by bit[10] of the
TX_RX_STS register. If the Rx MAC is disabled while it is in the process of receiving a frame, it goes to the IDLE
state after it completes the current frame reception.
Address Filtering
The Rx MAC offers several address filtering methods the user can employ to effectively block unwanted frames. It
also provides a Promiscuous mode, in which all supported filtering schemes are abandoned and the Rx MAC
transfers all the frames irrespective of the address they contain.
IPUG51_03.0, December 2010
20
Tri-Speed Ethernet MAC User’s Guide
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